A systolic INT8 NPU proven on real hardware — and two RISC-V SoCs that boot real operating systems.

A 2-D systolic array, parametrised in N. INT8 operands flow into N² multiply-accumulate cells; INT32 partial sums are requantised back to INT8 through a pipelined stage, then land in a register file that is memory-mapped to the host. Output-stationary, one weight per cell, and the whole thing scales by changing a parameter.

Two things make it worth taking seriously rather than admiring: the scaling is measured and law-like, and the design self-tests on power-up before it hands the bus to anything else.

Resource scaling — measured, reproduced by one command

NPU resource scaling with array size N

N = 2	8 wide MACs · 251 cells
N = 4	32 wide MACs · 720 cells
N = 8	128 wide MACs · 2,528 cells
N = 16	512 wide MACs · 9,488 cells

The array itself uses exactly N² wide INT8 multipliers — 4, 16, 64, 256 for N = 2, 4, 8, 16. The full design reports 2·N² because the requantise stage adds one scaling multiplier per output. Both the multiplier count and the cell count grow as O(N²). Reproduce any size with syn/yosys/bench_npu.sh 2 4 8 16; functional correctness at scale is checked by make -C sim npu and npu-big against a software reference.

Throughput — a model cross-checked against the RTL

One N×N output tile completes in 3N − 2 cycles in steady state (from the front-end skew schedule), performing up to N² MACs per cycle with every cell active. A 16×16 array therefore does 256 INT8 MACs/cycle at peak. The analytic model is checked against the finite-state machine in mm_frontend.v, not asserted.

Validated on hardware, not in simulation

Hardware validation results for the NPU

NPU, bare	131 / 131 INT8 matmuls PASS
Across	requantisation scales
Full SoC	RV32E core + native NPU bus · 7 / 7 vectors PASS
Read over	JTAG — power-on BIST owns the bus first, then releases it
Device	EP4CE10E22C8 · 10,320 LE · 46 DSP · C8 speed grade
Host link	Virtual-JTAG — reuses the programming cable, no extra pins

The self-checking vectors reproduce to 7/7 PASS, and the ABI between the compiler and the hardware was found wrong only on the board — an rv32i/RV32E mismatch plus a linker RAM-size error that no simulation run had reason to question. The raw Quartus map, fitter, static-timing and flow reports behind this summary are sent on request: these are the traces, not screenshots of them.

Reach — free tools, and a path off the FPGA

Toolchain reach for the NPU

FPGA flow	Quartus Prime Lite (free) · Yosys for technology-independent sizing
ASIC flow	OpenLane / OpenROAD → SkyWater 130 nm
ASIC synthesis	37,002 standard cells at N = 2 — synthesis, not a tape-out
Device ceiling measured	N = 8 is the practical fit on the KU3P; N = 16 overflows its 1,368 DSPs

No paid licence is required at any step, which is the point: an accelerator you can only build with an expensive toolchain is not an open platform. The ASIC figure is a synthesis result and is labelled as one — the tape-out path is documented and versioned, but nothing has been fabricated.

The substrate the NPU plugs into: two RISC-V platforms, both validated on hardware, at two different scales. One runs Linux out of DDR4; the other runs real SMP firmware on a board that costs less than a meal.

The platform targets the buyers that closed silicon excludes or overcharges: European research groups, integrators under GDPR and AI Act pressure, and anyone who needs a datapath they can actually read.

Two things that rarely meet are combined here. A reconfigurable systolic accelerator, proven on hardware and reproducible from a free toolchain. And a software-recompilable RISC-V core with an open, auditable instruction path — already proven up to a Linux userspace. Underneath both sits HBM-class bandwidth that most competing small accelerators simply do not have.

The design posture is deliberate about what this is not:

• Not a GPU competitor. On raw TOPS/$ and TOPS/W, dedicated edge-AI parts win, and any claim otherwise is marketing.
• Not a commodity edge-AI part. Camera-tile inference in volume belongs to Hailo and Axelera.
• Not a cloud service. It is a card and a toolchain, on your bench or in your rack.

What it wins on is the combination those alternatives cannot offer: an auditable open RTL path, a reconfigurable datapath, HBM-class bandwidth in a 75 W half-height card, and a provenance that stands up to a procurement filter written as "no third-country-controlled supplier".

Working notes, dated when the work lands — or labelled by the gate it closes. Threads still running are marked open.

1. 2026-06-26

   The NPU runs on hardware

   131/131 INT8 matmuls pass on an EP4CE10 across requantisation scales, read back over JTAG. The same day, a full RV32E SoC boots from on-chip memory, drives the NPU on its native bus, and self-checks 7/7 vectors — an ABI mismatch and a linker RAM-size error surfaced only on the board.

2. 2026-07-09

   BlackParrot fits a KU3P at 100 MHz

   A complete BlackParrot SoC closed timing on an XCKU3P. Kept as a reference point for what a manycore-oriented core costs on mid-range fabric.

3. 2026-08-04

   XiangShan: the estimate said 74 %, the measurement said 240 %

   An out-of-context synthesis of XiangShan's MinimalConfig reported 74 % of an XCKU3P's LUT6s. The real figure — a post-optimisation hierarchical report, on a larger device — was 520,681 LUTs against 216,960 available: 240 %. Stacking every optimistic lever (memories into BRAM, issue queues halved, predictors dropped, FPU and L3 removed) still lands near 291 K, above the 217 K budget, and the irreducible out-of-order core alone is ~350 K. MinimalConfig does not fit at any practical configuration. The port was tried on four platforms before the call was made to stop — and the estimate was wrong by roughly 3×, which only building it revealed.

4. 2026-08-19

   CVA6 takes the KU3P, and stalls in the kernel

   Boot hang localised to vfs_caches_init / mnt_init — the point where the kernel first needs working memory mapping. Useful precisely because it was wrong: it moved the target to a board with real RAM.

5. 2026-08-31

   Market and positioning study

   Four verticals scored on sales friction and willingness to pay. Conclusion: lead with academic and R&D prototyping, keep edge AI and defence behind it, do not attack the data centre.

6. 2026-09-01

   HBM FPGA sourcing audit

   Every FPGA with on-package HBM2/HBM2e compared on bandwidth, LUT count, price and lifecycle status. Alveo U50 selected as the scale-up reference.

7. open

   The CVA6 kernel still arrives over UART

   11 MB takes about 17 minutes at 115,200 baud — tolerable for bring-up, unusable for iteration. The same SD-boot approach now proven on the Ibex platform is the fix.

8. G3

   Standalone boot — FSBL in the Boot ROM

   A 4,130-byte bare-metal FSBL lives in BRAM and boots the payload itself: BRAM → SD card → validate → jump. The host programmed the FPGA and streamed nothing.

9. G4

   It boots on its own now

   The 16 MiB configuration flash was backed up first — full image, hash taken — then written, then verified by a real power-cycle with nothing else attached. That closes the chain end to end: RTL → SD card → filesystem → second stage → Boot ROM → flash. Seven gates, none skipped.

10. next

    Merge to gen1, then the accelerator into the fabric

    The two mature platform branches integrate into a single trunk, and from there the NPU moves from a proven standalone design into the memory-mapped slot already waiting for it.

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I am one engineer. If the scope is real, I will tell you what I can deliver and what I cannot — that conversation takes less time than a proposal.